Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns

ABSTRACT

Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of application Ser. No. 12/099,133, Titled “ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS” Filed Apr. 7, 2008.

This application is related to the following U.S. Patent Applications and Patents, which are herein incorporated by reference in their entirety: U.S. Pat. No. 8,244,718, filed on Aug. 27, 2007, entitled Methods and Systems for Hardware Acceleration of Database Operations and Queries, by Joseph I. Chamdani et al.; U.S. Pat. No. 7,908,259, filed on Aug. 27, 2007, entitled Hardware Acceleration Reconfigurable Processor for Accelerating Database Operations and Queries, by Jeremy Branscome et al.; U.S. patent application Ser. No. 11/895,997, filed on Aug. 27, 2007, entitled Processing Elements of a Hardware Acceleration Reconfigurable Processor for Accelerating Database Operations and Queries, by Jeremy Branscome et al.; U.S. patent application Ser. No. 12/168,821, filed on Jul. 7, 2008, entitled Methods and Systems for Generating Query Plans that are Compatible for Execution in Hardware, by Ravi Krishnamurthy et al.; U.S. patent application Ser. No. 12/099,076, filed on Apr. 7, 2008, entitled Methods and Systems for Run Time Scheduling Database Operations that are Executed in Hardware, by Joseph Chamdani et al.; U.S. Pat. No. 8,458,129, filed on Jun. 23, 2008, entitled Methods and Systems for Real Time Continuous Updates, by Kapil Surlaker et al.; and U.S. Pat. No. 7,966,343, filed on Apr. 7, 2008, entitled Accessing Data in a Column Store Based on Hardware Compatible Data Structures, by Liuxi Yang, et al; and U.S. Pat. No. 7,895,151, filed on Jun. 23, 2008, entitled Fast Batch Loading and Incremental Loading of Data into a Database, by James Shau, et. al.

BACKGROUND

Despite their different uses, applications, and workload characteristics, most systems run on a common Database Management System (DBMS) using a standard database programming language, such as Structured Query Language (SQL). Most modern DBMS implementations (Oracle, IBM DB2, Microsoft SQL, Sybase, MySQL, PostgreSQL, Ingress, etc.) are implemented on relational databases, which are well known to those skilled in the art.

Typically, a DBMS has a client side where applications or users submit their queries and a server side that executes the queries. On the server side, most enterprises employ one or more general purpose servers. However, although these platforms are flexible, general purpose servers are not optimized for many enterprise database applications. In a general purpose database server, all SQL queries and transactions are eventually mapped to low level software instructions called assembly instructions, which are then executed on a general purpose microprocessor (CPU). The CPU executes the instructions, and its logic is busy as long as the operand data are available, either in the register file or on-chip cache. To extract more parallelism from the assembly code and keep the CPU pipeline busy, known CPUs attempt to predict ahead the outcome of branch instructions and execute down the SQL code path speculatively. Execution time is reduced if the speculation is correct; the success of this speculation, however, is data dependent. Other state-of-the-art CPUs attempt to increase performance by employing simultaneous multithreading (SMT) and/or multi-core chip multiprocessing (CMP). To take advantage of these, changes have to be made at the application or DBMS source code to manually create the process/thread parallelism for the SMT or CMP CPUs. This is generally considered highly undesirable.

Unfortunately, general purpose CPUs are not efficient for database applications. Branch prediction is generally not accurate because database processing involves tree traversing and link list or pointer chasing that is very data dependent. Known CPUs employ the well known code-flow (or Von Neumann) architecture, which uses a highly pipelined instruction flow (rather than a data-flow where operand data is pipelined) to operate on data stored in the CPUs tiny register files. Real database workloads, however, typically require processing Gigabytes to Terabytes of data, which overwhelms these tiny registers with loads and reloads. On-chip cache of a general purpose CPU is not effective since it's relatively too small for real database workloads. This requires that the database server frequently retrieve data from its small memory or disk. Accordingly, known database servers rely heavily on squeezing the utilization of their small system memory size and disk input/output (I/O) bandwidth. Those skilled in the art recognize that these bottlenecks between storage I/O, the CPU, and memory are very significant performance factors.

However, overcoming these bottlenecks is a complex task because typical database systems consist of several layers of hardware, software, etc., that influence the overall performance of the system. These layers comprise, for example, the application software, the DBMS software, operating system (OS), server processor systems, such as its CPU, memory, and disk I/O and infrastructure. Traditionally, performance has been optimized in a database system horizontally, i.e., within a particular layer. For example, many solutions attempt to optimize various solutions for the DBMS query processing, caching, the disk I/O, etc. These solutions employ a generic, narrow approach that still fails to truly optimize the large performance potentials of the database system, especially for relational database systems having complex read-intensive applications.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the figures:

FIG. 1 illustrates an exemplary system that is consistent with the principles of the present invention;

FIG. 2 illustrates exemplary system topologies that are consistent with the principles of the present invention;

FIG. 3A illustrates a prior art database system and FIG. 3B illustrates some of the optimizations of the present invention over the prior art;

FIG. 4 illustrates a functional architecture of the custom computing (C2) software of the present invention;

FIG. 5 illustrates a protocol stack employed by the C2 software and a Hardware Accelerated Reconfigurable Processor (HARP) of the present invention;

FIG. 6 illustrates an exemplary architecture of a HARP;

FIG. 7 illustrates a column store database and associated data structures employed by some embodiments of the present invention;

FIG. 8 illustrates a table column layout and associated data structures employed by some embodiments of the present invention;

FIG. 9 illustrates an exemplary machine code database instruction flow for a SQL query that is consistent with the principles of the present invention;

FIG. 10 illustrates an exemplary dataflow for a SQL query through processing elements in the HARP in accordance with the principles of the present invention;

FIG. 11 illustrates an exemplary logic flow of the addressing schemes employed in the present invention;

FIG. 12 illustrates a structure of the global database virtual address scheme of the present invention;

FIG. 13 illustrates a general architecture of the hardware-friendly data structures of the present invention;

FIG. 14 illustrates an indexing framework that is hardware-friendly in accordance with the principles of the present invention;

FIG. 15 illustrates an exemplary hit list employed by the present invention;

FIG. 16 illustrates traversal of a hit list node;

FIG. 17 illustrates exemplary group indexing by the present invention;

FIG. 18 illustrates an exemplary reverse index;

FIG. 19 illustrates an exemplary word dictionary compare that utilizes the hardware compatible data structures; and

FIG. 20 illustrates an exemplary forward index.

DETAILED DESCRIPTION

Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.

Due to the comprehensive nature of the present inventions in the C2 solution, the figures are presented generally from a high level of detail and progress to a low level of detail. For example, FIGS. 1-3 illustrate exemplary systems and topologies enabled by the present invention. FIGS. 4-5 illustrate the architecture of the C2 software. FIG. 6 illustrates the architecture of a HARP module. FIGS. 7-8 illustrate the database format and data structures employed by the C2 solution of the present invention. FIGS. 9-10 illustrate an example execution of a SQL query by the C2 solution of the present invention. FIGS. 11-12 illustrate the use and architecture of the global database virtual addressing scheme employed by the present invention. FIGS. 13-19 are then provided to illustrate various hardware-friendly data structures of the present invention.

Reference will now be made in detail to the exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 1—An Exemplary C2 System

The present invention employs a custom computing (C2) solution that provides a significant gain in performance for enterprise database applications. In the C2 solution, a node or appliance may comprise the host (or base) system that is combined with hardware acceleration reconfigurable processors (HARP). These HARPs are specially designed to optimize the performance of database systems and its applications, especially relational database systems and read-intensive applications.

A host system may be any standard or pre-existing DBMS system. In general, such systems will comprise a standard general purpose CPU, a system memory, I/O interfaces, etc.

The HARPs are coupled to the host system and are designed to offload repetitive database operations from the DBMS running on the host system. The HARPs utilize dataflow architecture processing elements that execute machine code instructions that are defined for various database operations. The C2 solution may employ a node that is scalable to include one HARP, or multiple HARPs. In addition, the C2 solution may use a federated architecture comprising multiple nodes, i.e., multiple DBMS servers that are enhanced with the C2 solution.

In some embodiments, the C2 solution employs an open architecture and co-processor approach so that the C2 hardware can be easily integrated into existing database systems. Of note, the hardware acceleration of the C2 solution utilizes novel machine code database instructions to execute certain fragments of a query in a dataflow and using parallel, pipelined execution.

In the present invention, the C2 solution also comprises software that orchestrates the operations of the DBMS running on the host system and the HARPs. The C2 software is configured with a flexible, layered architecture to make it hardware and database system agnostic. Thus, the C2 software is capable of seamlessly working with existing DBMSs based on this open architecture.

In general, the C2 software receives the query from the DBMS and breaks the query down into query fragments. The C2 software then decides which of these query fragments can be appropriately handled in software (in the C2 software itself or back in the originating DBMS) or, ideally, with hardware acceleration in the HARPs. All or part of the query may be processed by the C2 software and HARPs.

In addition, in order to maximize the efficiency of the hardware acceleration, the C2 solution stores its databases in compressed, column-store format and utilizes various hardware-friendly data structures. The C2 solution may employ various compression techniques to minimize or reduce the storage footprint of its databases. The column-store format and hardware-friendly data structures allow the HARPs or C2 software to operate directly on the compressed data in the column-store database. The column-store database may employ columns and column groups that are arranged based on an implicit row identifier (RID) scheme and RID to primary key column mapping to allow for easy processing by the HARPs. The hardware-friendly data structures also allow for efficient indexing, data manipulation, etc. by the HARPs.

For example, the C2 solution utilizes a global virtual address space for the entire database to greatly simplify and maximize efficiency of create, read, update, and delete operations of data in a database. In some embodiments, the columns and column groups are configured with a fixed width to allow for arithmetic memory addressing and translation from a virtual address to a physical memory address. On-demand and speculative prefetching may also be utilized by the C2 solution to hide I/O bandwidth latency and maximize HARP utilization.

Referring now to FIG. 1, an exemplary system 100 of the C2 solution is illustrated. As shown, system 100 may comprise an application 102 that is running on a client 104, such as a personal computer or other system. Application 102 interfaces a DBMS 106 across a network 108, such as the Internet, local area network, etc. DBMS 106 may further interface one or more databases stored in storage infrastructure 112. For purposes of explanation, DBMS 106 and its components may be collectively referred to in this disclosure as a node of system 100. Although FIG. 1 shows a single node, system 100 may of course comprise multiple nodes. The various components of FIG. 1 will now be further described.

Application 102 may be any computer software that requests the services of DBMS 106. Such applications are well known to those skilled in the art. For example, application 102 may be a web browser in which a user is submitting various search requests. Of course, application 102 may be another system or software that is consuming the services of DBMS 106 and submitting queries to DBMS 106.

Client 104 represents the hardware and software that supports the execution of application 102. Such clients are well known to those skilled in the art. For example, client 104 may be a personal computer or another server.

DBMS 106 is any computer software that manages databases. In general, DBMS 106 controls the organization, storage, management, and retrieval of data in a database. As is well known, these types of systems are common for supporting various SQL queries on relational databases (and thus may also be known as a RDBMS). Due to its open architecture, various DBMS systems may be employed by the present invention. Typical examples of DBMSs include Oracle, DB2, Microsoft Access, Microsoft SQL Server, PostgreSQL, and MySQL.

In some embodiments, and for purposes of explanation, DBMS 106 is shown comprising C2 software 110 interfacing MySQL software 114 via an API 116. MySQL software 114 is open source software that is sponsored and provided by MySQL AB and is well known to those skilled in the art. Of course, any DBMS software, such as those noted above, may be employed in the present invention.

C2 software 110 orchestrates the execution of a query forwarded from DBMS 106, and thus, operates in conjunction with MySQL software 114. For example, in the C2 software 110, SQL queries are broken down into query fragments and then routed to the most appropriate resource. A query fragment may be handled in C2 hardware, i.e., HARP module 204. (HARP module 204 is further described with reference to FIG. 2.) The query fragment may also be processed in the C2 software itself, or returned for handling by MySQL software 114.

In general, C2 software 110 utilizes a flexible, layered architecture to make it hardware and database system agnostic. For example, C2 software 110 may operate as a storage engine of MySQL software 114. As is well known, MySQL software 114 may provide an API 116 for storage engines, which can interface with C2 software 110. API 116 comprises the software that specifies how the C2 software 110 and MySQL software 114 will interact, how they will request services from each other, such as SQL queries and results.

As a storage engine, C2 software 110 may employ the MySQL API 116 to provide various storage mechanisms, indexing facilities, locking levels, and ultimately provide a range of different functions and capabilities that are transparent to MySQL software 114. As noted above, this is one aspect of how the present invention overcomes the generic approach in known solutions without having to sacrifice performance for functionality, or fine tune the database. Of note, although FIG. 1 shows a single storage engine, MySQL software 114 may be coupled to multiple storage engines (not shown) in addition to C2 software 110. C2 software 110 is also described in further detail with reference to FIGS. 4-5.

Network 108 represents the communication infrastructure that couples application 102 and DBMS 106. For example, network 108 may be the Internet. Of course, any network, such as a local area network, wide area network, etc., may be employed by the present invention.

Storage infrastructure 112 comprises the computer storage devices, such as disk arrays, tape libraries, and optical drives that serve as the storage for the databases of system 100. Storage infrastructure 112 may employ various architectures, such as a storage area network, network attached storage, etc., which are known to those skilled in the art.

In some embodiments, the C2 solution stores its databases in storage infrastructure 112 in column-store format. Column-store format is where data is stored in columns or groups of columns. Column-store format is advantageous for data fetching, scanning, searching, and data compression. The column-store format may employ fixed width columns and column groups with implicit RIDs and a RID to primary key column to allow for arithmetic memory addressing and translation. This allows HARPs 204 to utilize hardware processing for database processing, such as column hopping, and to operate directly on the compressed data in the columns.

In contrast, in typical DBMS environments, data is stored in row-store format. Row-store format is sometimes considered by those skilled in the art for having better performance in data updates and record retrieval; thus, it is sometimes considered to have better functionality over column-store databases in most applications with a high ratio of updates over reads. In the present invention, however, the C2 solution achieves better performance by using hardware acceleration with a column-store database, yet it still delivers the functionality and benefits of row-store databases. The column store format used by the C2 solution of the present invention is further described with reference to FIGS. 7-8.

FIG. 2—System Topologies

FIG. 2 illustrates exemplary system topologies that are consistent with the principles of the present invention. As shown, FIG. 2 illustrates a basic C2 node topology, a scale up C2 node topology, and a scale out topology. These various topologies may be utilized to customize the C2 solution for various sizes of databases and desired performance. In addition, these topologies are provided to illustrate that the C2 solution can be easily scaled up to virtually any size of database or performance.

First, the basic C2 node will be explained, which comprises a single host system 202 and a single HARP module 204. Variations of this basic node will then be explained to show how the basic node can be scaled up and how multiple nodes can be employed in a federated architecture.

The basic C2 node topology may comprise a host system 202 and a hardware acceleration reconfigurable processor (HARP) module 204. Collectively, host 202 and HARP module 204 may be referred to as a node or appliance. In some embodiments, host system 202 and HARP module 204 are coupled together over a known communications interface, such as a PCIe or hypertransport (HT) interface. In terms of packaging, host system 202 and HARP module 204 may be built on one or more cards or blades that are bundled together in a common chassis or merely wired together. In the C2 solution, host system 202 and HARP module 204 may be flexibly packaged using a modular form factor for ease of installation and scaling.

The host system 202 may comprise a general purpose CPU, such as a Xeon x86 processor by the Intel Corporation, and a memory, such as a dynamic random access memory. Such types of host systems are well known to those skilled in the art. In general, in the C2 solution, host system 202 will be used to process parts of a query that are less time consuming (i.e., slow path portion), such as server-client connection, authentication, SQL parsing, logging, etc. However, in order to optimize performance, the bulk of query execution (i.e., the fast path portion) is offloaded to the HARP module 204.

Host system 202 may run MySQL software 114 and also run C2 software 110 that orchestrates query processing between MySQL 114 and HARP 204. In particular, C2 software 110 will decompose a query into a set of query fragments. Each fragment comprises various tasks, which may have certain dependencies. C2 software 110 will determine which fragments and tasks are part of the fast path portion and offload them to the HARP module 204. Appropriate tasks for the selected query fragments are sent to HARP module 204 with information on the database operation dependency graph. Within the HARP module 204, tasks are further broken down into parallel/pipelined machine code operations (known as MOPs) and executed in hardware.

HARP module 204 comprises processing logic (HARP logic 302) and a relatively large memory (HARP memory 304) for hardware accelerating database operations of the node. In some embodiments, HARP module 204 is configured to handle various repetitive database tasks, such as table scanning, indexing, etc. In the C2 solution, HARP module 204 can receive high-level database query tasks (not just low-level read/write or primitive computation tasks as is typical for a general purpose processor) in the form of machine code database instructions.

HARP logic 302 is the hardware that executes machine code database instructions for the database tasks being handled by HARP module 204. To adapt to application requirement changes, the HARP logic 302 is designed to have hardware re-configurability. Accordingly, in some embodiments, HARP logic 302 is implemented using field programmable gate arrays (FPGAs). However, any type of custom integrated circuit, such as application specific integrated circuits (ASICs), may be implemented as HARP logic 302.

HARP memory 304 serves as the memory of HARP module 204. In order to maximize the efficiency of the HARP logic 302, the HARP memory 304 may be implemented using relatively large amounts of memory. For example, in some embodiments, the HARP memory 304 in a HARP module 204 may comprise 256 gigabytes or more of RAM or DRAM. Of course, even larger amounts of memory may be installed in HARP module 204. HARP logic 302 and HARP memory 304 are further described with reference to FIG. 6.

In addition to the basic C2 node, a scale up C2 node topology may be used as an extension of the basic C2 node. As shown, host system 202 may now be coupled to a plurality or array of 1-N HARP modules 204. In this type of node, a PCIe switch or other suitable switching fabric may couple these components together with storage infrastructure 112. Of course, other internal arrangements for a scale up C2 node may be utilized in the present invention.

Going further, a scale out topology can be used for multiple C2 nodes. As shown, the scale out topology may comprise various combinations of either the basic or scale up C2 nodes. For example, as shown, the scale out topology may comprise Nodes 1-M, which are coupled to storage infrastructure 112. In FIG. 2, Node 1 is shown as a basic C2 node, while Node M is shown as a scale up node. A control node 206 is also shown and manages the operations of Nodes 1-M. Control node 206 is shown as a separate node; however, those skilled in the art will recognize the role of control node 206 by any of Nodes 1-M. Other variations in node hierarchy and management are within the scope of the present invention. Of course, this topology may also comprise a variety of combinations of nodes.

FIGS. 3A and 3B—Some Advantages

FIG. 3A illustrates a prior art database system and FIG. 3B illustrates an exemplary implementation of the C2 solution for the present invention. In FIG. 3A, a typical prior art database system is shown. An SQL query is submitted to a DBMS (e.g., MySQL), which runs on top of a typical operating system. The CPU attempts to then execute the SQL query. However, because the CPU is a general purpose CPU it executes this query based on software, which has several limitations.

In contrast, as shown in FIG. 3B, the SQL query may submitted to a C2 system having a DBMS that comprises a top layer DBMS software (i.e., MySQL) 114 and C2 software 110. C2 software 110 interfaces with the DBMS software 114 to orchestrate and optimize processing of the SQL query.

In particular, C2 software 110 may identify portions of the query, i.e., the fast path portion, which is better handled in hardware, such as HARP module 204. Such portions may be those fragments of the query that are repetitive in nature, such as scanning, indexing, etc. In the prior art system, the DBMS is limited by its own programming, the operating system, and the general purpose CPU. The present invention avoids these bottlenecks by offloading fast path portions of a query to HARP module 204.

As shown, HARP module 204 comprises HARP logic 302 and a HARP memory 304 to accelerate the processing of SQL queries. In order to maximize the use of HARP module 204, the present invention may also utilize column store databases. Whereas the prior art system is hindered by the limitations of a standard row store database. These features also allow the present invention to maximize the performance of the I/O between the operating system and storage.

For ease of implementation, C2 software 110 may be implemented on well known operating systems. The operating system will continue to be used to perform basic tasks such as controlling and allocating memory, prioritizing system requests, controlling input and output devices, facilitating networking, and managing files and data in storage infrastructure 112. In some embodiments, various operating systems, such as Linux, UNIX, and Microsoft Windows, may be implemented.

FIGS. 3A and 3B are provided to illustrate some of the differences between the present invention and the prior art and advantages of the present invention. Those skilled in the art will also recognize that other advantages and benefits may be achieved by the embodiments of the present invention. For purposes of explanation, the present disclosure will now describe the C2 software, hardware, data structures, and some operations in further detail.

FIG. 4—C2 Software Architecture

As noted, C2 software 110 orchestrates the processing of a query between MySQL software 114 and HARP module 204. In some embodiments, C2 software 110 runs as an application on host system 202 and as a storage engine of MySQL software 114. FIG. 4 illustrates an architecture of the C2 software 110. As shown, C2 software 110 comprises a query and plan manager 402, a query reduction/rewrite module 404, an optimizer 406, a post optimizer module 408, a query plan generator 410, an execution engine 412, a buffer manager 414, a task manager 416, a memory manager 418, a storage manager 420, an answer manager 422, an update manager 424, shared utilities 426, and a HARP manager 428. Each of these components will now be briefly described.

Query and plan manager 402 analyzes and represents the query received from the MySQL software 114, annotates the query, and provides a representation of the query plan. Query reduction/rewrite module 404 breaks the query into query fragments and rewrites the query fragments into tasks. Rewrites may be needed for compressed domain rewrites and machine code database instruction operator rewrites. Optimizer 406 performs cost-based optimization to be done using cost model of resources available to C2 software 110, i.e., HARP module 204, resources of C2 software 110 itself using software operations, or MySQL software 114.

These modules interact with each other to determine how to execute a query, such as a SQL query from MySQL software 114. The data structures output by the query plan generator 410 will be the same data structure that the optimizer 406 and the rewrite module 404 will operate on. Once a parsed SQL query has been represented in this data structure (converted, for example, from MySQL), manager 402 rewrites the query such that each fragment of the query can be done entirely in MySQL software 114, in C2 software 110, or in HARP module 204. Once the final query representation is available, the rewrite module 404 goes through and breaks the graph into query fragments.

Post optimizer module 408 is an optional component that rewrites after the optimizer 406 for coalescing improvements found by optimizer 406. Query plan generator 410 generates an annotations-based, template-driven plan generation for the query tasks. Execution engine 412 executes the query fragments that are to be handled by software or supervises the query execution in HARP module 204 via HARP manager 428.

Buffer manager 414 manages the buffers of data held in the memory of host 202 and for the software execution tasks handled by host 202. Task manager 416 orchestrates the execution of all the tasks in HARP module 204 and software, i.e., in execution engine 412 or MySQL software 114. Task manager 416 is further described below.

Memory manager 418 manages the virtual address and physical address space employed by C2 software 110 and HARP module 204 in HARP memory 304. In some embodiments, memory manager 418 utilizes a 50-bit VA addressing (i.e., in excess of 1 petabyte). This allows C2 software 110 to globally address an entire database and optimize hardware execution of the query tasks. An example of the addressing scheme that may be employed is further described below.

Storage manager 420 is responsible for managing transfers of data from HARP memory 304 to/from storage infrastructure 112. Answer manager 422 is responsible for compiling the results of the query fragments and providing the result to MySQL software 114 via the API 116.

Update manager 424 is responsible for updating any data in the database stored in storage infrastructure 112. Shared utilities 426 provide various utilities for the components of C2 software 110. For example, these shared utilities may include a performance monitor, a metadata manager, an exception handler, a compression library, a logging and recovery manager, and a data loader.

HARP manager 428 controls execution of the tasks in HARP module 204 by setting up the machine code database instructions and handles all interrupts from any of the hardware in HARP module 204. In some embodiments, HARP manager 428 employs a function library known as a Hardware Acceleration Function Library (HAFL) in order to make its function calls to HARP module 204. One of the functions of the HAFL is task pipelining and IMC extension and overflow.

FIG. 5—Protocol Stack of C2 Software

As shown, a SQL query is received in the RDBMS layer, i.e., MySQL software 114. MySQL software 114 then passes the SQL query via API 116 to C2 software 110. In C2 software 110, the SQL query is processed and executed. At this layer, C2 software 110 also manages retrieving data for the SQL query, if necessary, from storage infrastructure 112 or from host system 202.

In order to communicate with HARP module 204, HARP manager 428 employs the HAFL layer in order to make its function calls to HARP module 204. In order to allow for variances in hardware that may exist in HARP module 204, the protocol stack may also comprise a hardware abstraction layer. Information is then passed from C2 software 110 to HARP module 204 in the form of machine code database instructions via an interconnect layer. As noted, this interconnect layer may be in accordance with the well known PCIe or HT standards.

Within HARP module 204, the machine code database instructions are parsed and forwarded to HARP logic 302. These instructions may relate to a variety of tasks and operations. For example, as shown, the protocol stack provides for systems management, task coordination, and direct memory access to HARP memory 304. In HARP logic 302, machine code database instructions can be executed by the various types of processing elements (PE). HARP logic 302 may interface with HARP memory 304, i.e., direct memory access by utilizing the memory management layer.

FIG. 6—HARP Logic

FIG. 6 illustrates an exemplary architecture of the HARP logic 302. As shown, HARP logic 302 may comprise a set of processing cores 602, 604, 606, and 608, and switching fabric 610. Processing core 602 (as well as cores 604, 606, and 608) may comprise a set of processing elements (PEs) 620. In the embodiment shown, processing cores 602, 604, 606, and 608 each comprise two PEs; of course, each processing core may comprise any number of PEs.

In addition to its PEs, processing core 602 may comprise a task processor 612, a memory manager 614, a buffer cache 616, and an interconnect 618. One or more of these components may be duplicated or removed from the other processing cores 604, 606, and 608. For example, as shown, core 602 may be the sole core that includes task processor 612 and an interconnect 618. This architecture may be employed because cores 602, 604, 606, and 608 are connected via switching fabric 610 and may operate logically as a single processor or processor core. Of course, one skilled in the art will recognize that various redundancies may be employed in these processing cores as desired.

Task processor 612 is the hardware that supervises the operations of the processing cores 602, 604, 606, and 608. Task Processor 612 is a master scheduling and control processing element, disconnected from the direct dataflow of the execution process for a query. Task processor 612 maintains a running schedule of machine code database instructions which have completed, are in progress, or are yet to execute, and their accompanying dependencies. The task processor 612 may also dispatch machine code database instructions for execution and monitor their progress. Dependencies can be implicit, or explicit in terms of strong intra- or inter-processor release criteria. Machine code database instructions stalled for software-assist can be context-switched by the Task Processor 612, which can begin or continue execution of other independent query tasks, to optimize utilization of execution resources in HARP logic 302.

Memory manager 614 is the hardware that interfaces HARP memory 304. For example, memory manager 614 may employ well known memory addressing techniques, such as translation look-aside buffers to map the global database virtual address space to a physical address in HARP memory 304 to access data stored in HARP memory 304.

Buffer cache 616 serves as a small cache for a processing core. For example, temporary results or other meta-data may be held in buffer cache 616.

PCIe interconnect 618 is the hardware that interfaces with host system 202. As noted, interconnect 618 may be a PCIe or HT interconnect.

PEs 620 represent units of the hardware and circuitry of HARP logic 302. As noted, PEs 620 utilize a novel dataflow architecture to accomplish the query processing requested of HARP logic 302. In particular, PEs 620 implement execution of an assortment of machine code database instructions that are known as Macro Ops (MOPs) and Micro Ops (UOPs). MOPs and UOPs are programmed and executed by the PEs 620 to realize some distinct phase of data processing needed to complete a query. MOPs and UOPs are just example embodiments of machine code database instructions; other types of instruction sets for high level database operations of course may be used by the C2 solution.

PEs 620 pass logical intermediate MOP results among one another through a variable-length dataflow of dataflow tokens, carried across an interconnect data structure (which is a physical data structure and not a software data structure) termed an Inter-Macro Op Communication (IMC) path. Of note, the IMC paths and self routing fabric 610 allow HARP module 204 to utilize a minimal amount of reads/writes to HARP memory 304 by keeping most intermediate results flowing through the IMCs in a pipelined, parallel fashion. Data passed in an IMC may be temporarily stored in buffer caches 616 and interconnect fabric 610; however, data in IMCs can also be dispatched out through interconnect 618 to other PEs 620 on another HARP module.

In the dataflow concept, each execution step, as implemented by a MOP and its accompanying UOP program, can apply symmetrically and independently to a prescribed tuple of input data to produce some tuple of result. Given the independence and symmetry, any number of these tuples may then be combined into a list, matrix, or more sophisticated structure to be propagated and executed in pipelined fashion, for optimal execution system throughput. These lists of tuples, comprised fundamentally of dataflow tokens, are the intermediate and final results passed dynamically among the MOPs via IMC.

Although the dataflow travels over physical links of potentially fixed dimension, the logical structure of the contents can be multi-dimensional, produced and interpreted in one of two different ways: either with or without inherent, internal formatting information. Carrying explicit internal formatting information allows compression of otherwise extensive join relationships into nested sub list structures which can require less link bandwidth from fabric 610 and intermediate storage in buffer cache 616, at the cost of the extra formatting delimiters, increased interpretation complexity and the restriction of fixing the interpretation globally among all consumers. Without inherent formatting, a logical dataflow may be interpreted by the consumer as any n-dimensional structure having an arbitrary but consistent number of columns of arbitrary but consistent length and width. It should be noted that the non-formatted form can be beneficial not only in its structural simplicity, but in the freedom with which consumer MOPs may interpret, or reinterpret, its contents depending upon the purpose of the execution step a consumer is implementing.

The dataflow used in realizing a given query execution can be described by a directed acyclic graph (DAG) with one intervening MOP at each point of flow convergence and bifurcation, one MOP at each starting and ending point, as well as any point necessary in between (i.e. single input & output MOP). The DAG must have at least one starting and one ending point, although any larger number may be necessary to realize a query. MOPs which serve as the starting point are designed to begin the dataflow by consuming and processing large amounts of data from local storage. Ending point MOPs may terminate the dataflow back into local storage, or to a link which deposits the collected dataflow (result table list) into host CPU memory. An example of a DAG for a well known TPC-H query is shown in FIG. 9.

As mentioned above, MOP DAGs can physically and logically converge or bifurcate, programmatically. The physical convergence is accomplished with a multi-input MOP, which relate inputs in some logical fashion to produce an output comprised of all inputs (e.g. composition, merge, etc.). The physical bifurcation is accomplished by means of multicast technology in the IMC fabric, which dynamically copies an intermediate result list to multiple consumer MOPs. These mechanisms work together to allow realization of any desired DAG of MOP execution flow.

In the present invention, each MOP is configured to operate directly on the compressed data in the column-store database and realizes some fundamental step in query processing. MOPs are physically implemented and executed by PEs 620 which, depending on specific type, will realize a distinct subset of all MOP types. MOPs work systematically on individual tuples extracted either from local database storage in HARP memory 304 or the IMC dataflow, producing output tuples which may be interpreted by one or more MOP processes downstream.

UOPs are the low-level data manipulators which may be combined into a MOP-specific UOP program accompanying a MOP, to perform analysis and/or transformation of each tuple the MOP extracts. MOPs which utilize UOP programs are aware of the dependency, distributing selected portions of each tuple to the underlying UOP engine, extant within all PEs 620 supporting such MOPs. For each set of inputs from each tuple, the UOP program produces a set of outputs, which the MOP may use in various ways to realize its function.

For example, one manner a MOP may use UOP output is to evaluate each tuple of a list of tuples for a set of predicating conditions, where the MOP decides either to retain or to drop each tuple based on the UOP result. Another manner is for the UOP to perform an arithmetic transformation of each input tuple, where the MOP either appends the UOP result to form a larger logical tuple, or replaces some portion of the input tuple to form the output tuple.

Given a finite number of execution resources in PEs 620, the full MOP dataflow DAG needed to execute a query may be partitioned into segments of connected MOPs called tasks. These tasks are then scheduled by task processor 612 for execution in a sequential fashion, as MOP execution resources become available in PEs 620. Significant in this process is the propagation of the execution dataflow among these tasks, such that the entire query result is accurately and consistently computed, regardless of how each task is apportioned and regardless of the latency between scheduling each task.

One method that may be employed in HARP logic 302 is to treat each task atomically and independently, terminating the dataflow back into local storage in HARP memory 304 at the end of each task and restarting that dataflow at the beginning of the subsequent task by reloading it from HARP memory 304. In some embodiments, a more efficient method may be employed to pipeline tasks at their finer, constituent MOP granularity, where at least one MOP of a new task may begin execution before all MOPs of the previous task have finished. This fine-grained method is referred to as task pipelining.

Keeping the dataflow alive over task boundaries is a key to realizing the extra efficiency of task pipelining. To accomplish this in the C2 solution, IMCs may include the ability to dynamically spill, or send their dataflow to an elastic buffer backed by HARP memory 304, pending the awakening of a consumer MOP which will continue the dataflow. On scheduling the consumer MOP, IMCs are able to fill dynamically, reading from the elastic buffer in HARP memory 304 as necessary to continue execution, pulling out any slack that may have built up in the dataflow while waiting for the scheduling opportunity. Task pipelining with these mechanisms then may provide a more efficient use of execution resources, down to the MOP granularity, such that a query may be processed as quickly as possible.

Due to the sheer volume of data involved, high-latency, low-bandwidth, non-volatile storage in storage infrastructure 112 often holds most of the data being queried. Because execution rates can outstrip the bandwidth available to read from such storage, tasks requiring latent data can shorten execution time by starting and progressing their dataflow execution at the rate the data arrives, instead of waiting for an entire prefetch to complete before beginning execution. This shortcut is referred to as prefetch pipelining. The C2 solution may employ both on-demand prefetching and speculative prefetching. On-demand prefetching is where data is prefetched based on the progress of the dataflow. Speculative prefetching is where data is prefetched based on an algorithm or heuristic that estimates the data is likely to be requested as part of a dataflow.

In the present invention, prefetch pipelining can be accomplished by having one or more MOPs, when beginning a task's dataflow, accept data progressively as it is read from slow storage in storage infrastructure 112. IMCs are capable of filling progressively as data arrives, as are all MOPs already designed to read from local storage in HARP memory 304. Given that support, MOPs can satisfy the requirement of executing progressively at the rate of the inbound dataflow and accomplish efficient prefetch pipelining.

As shown, processing core 602 may comprise scanning/indexing PE 622 and XCAM PE 624 as its set of PEs 620. As noted, PEs 620 are the physical entities responsible for executing MOPs, with their underlying UOPs, and for realizing other sophisticated control mechanisms. Various incarnations of processing elements are described herein, where each incarnation supports a distinct subset of the MOP and control space, providing different and distinct functionality from the perspective of query execution. Each of the different PE forms is now addressed where those which support MOPs employing UOP programs implicitly contain a UOP processing engine.

Scanning/Indexing PE 622 implements MOPs which analyze database column groups stored in local memory, performing parallel field extraction and comparison, to generate row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy the applied predicate. For some MOP forms, a data value list (which is an abstract term for a logical tuple list flowing through an IMC) containing a column of potentially sparse row pointers may be given as input, in which case the scan occurs over a sparse subset of the database. For other forms, scanning occurs sequentially over a selected range of rows.

The selection predicate is stipulated through a micro-op (UOP) program of finite length and complexity. For conjunctive predicates which span columns in different column groups, scanning may be done either iteratively or concurrently in dataflow progression through multiple MOPs to produce the final, fully selected row pointer list.

Inasmuch as the Scanning/Indexing PE 622 optimizes scanning parallelism and is capable of constructing and interpreting compacted bitmap bundles of row pointers (which are a compressed representation of row pointers, sparse or dense, that can be packed into logical tuples flowing through an IMC), it operates most efficiently for highly selective predicates, amplifying the benefits thereof. Regardless, its MOP support locates specific database content.

Scanning/Indexing PE 622 also implements MOPs which project database column groups from HARP memory 304, search and join index structures, and manipulate in-flight data flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results. Depending on the MOP, input can be one or more value lists whose content may be interpreted in a one- or two-dimensional manner, where two-dimensional lists may have an arbitrary number of columns (which may have arbitrary logical width).

In the context of list reduction, a UOP program of finite length and complexity is stipulated as a predicate function, to qualify one or more components of the input value list elements, eliminating tuples that do not qualify. List composition involves the combining of related lists into a single output format which explicitly relates the input elements by list locality, while list merging involves intermingling input tuples of like size in an unrelated order. Modification of lists involves a UOP program, which can generate data-dependent computations, to replace component(s) of each input tuple.

The Scanning/Indexing PE 622 may also be used for joins with indexes, like a Group Index, which involves the association of each input tuple with potentially many related data components, in a one-to-many mapping, as given by referencing the index via a row pointer component contained in each input tuple. MOPs implemented by the Scanning/Indexing PE 622 may thus relate elements of a relational database by query-specific criteria, which can be useful for any query of moderate to advanced complexity.

XCAM PE 624 implements MOPs which perform associative operations, like accumulation and aggregation, sieving, sorting and associative joins. Input is in the form of a two-dimensional data value list which can be interpreted as containing at least two columns related by list locality: key and associated value.

Accumulation occurs over all data of like keys (associatively), applying one of several possible aggregation functions, like summation or an atomic compare and exchange of the current accumulator value with the input value component. A direct map mode exists which maps the keys directly into HARP memory 304, employing a small cache (not shown) to minimize memory access penalties. A local mode of accumulation exists, as well, to realize zero memory access penalties by opportunistically employing the cache, at the risk of incomplete aggregation.

Sieving involves the progressive capture of keys qualifying as most extreme, according to a programmable sieving function, generating a result list of the original input keys and values such that the last N tuples' keys are the most extreme of all keys in the original input. Iterative application of Sieve can converge on a sorted output, over groups of some small granularity.

Sorting can also be accomplished through construction and traversal of either hashes or B-Trees. These hashes or B-Trees can be constructed to relate each input key to its associated value with a structure that is efficient to search and with which to join.

Within each of PEs 620 thus may be a UOP Processing Engine (not shown). Whereas PEs 620 execute MOPs in a dataflow fashion at the higher levels, embedded UOP Processing Engines in PEs 620 realize the execution of UOPs, which embed within their logical MOP parent to serve its low-level data manipulation and analysis needs. In some embodiments, the UOP processing engine is code-flow logic, where a UOP program is executed repetitively by a parent Processing Element at MOP-imposed boundaries, given MOP-extracted input data, to produce results interpreted by the parent MOP.

Considering the code-flow nature, each UOP engine has its own program storage, persistent register set and execution resources. It is capable, through appropriate UOP instructions, to accept data selected from the parent MOP and to simultaneously execute specified data manipulation or analysis thereon, in combination with some stored register state. In this manner, this tiny code-flow processor is able to fit seamlessly into the dataflow as a variable-latency element which, at the cost of increased latency, is capable of performing any of the most complex low-level data manipulation and analysis functions on the dataflow pouring through. The capability of the MOP to select and present only those data required for UOP processing, at a fine granularity, minimizes the latency imposed by the UOP code flow, maximizing overall dataflow throughput.

FIG. 7—C2 Data Structures

The C2 solution utilizes various hardware-friendly data structures to assist in hardware accelerating database operations by HARP modules 204. As described below in Table 1, the C2 solution may employ three different columns. These columns enable efficient utilization of HARP logic 302 and HARP memory 304, and bandwidth and disk bandwidth with storage infrastructure 112.

TABLE 1 Column Formats Name Description Packed All rows in the column are packed consecutively. All rows Column have a uniform size in each column. A packed column can be disk-resident or memory-resident. The packed Column can be sorted with respect to the primary key. Sorted- This is for the date columns. The date is stored in Compressed the form of running length. Each date has an entry for Column recording its starting count and ending count. The offset could be zero if the date does not have any item in the table. It companion column can be accessed with staring and ending counts. Companion The companion table links the Sorted-Compressed Column Column to other columns.

In general, hot columns (i.e., columns having active or frequent access) stay in the HARP memory 304 so that they can be accessed randomly fast. Warm Columns (i.e., columns having less active access) also stay in the HARP memory 304; but occasionally, they may be evicted to a disk in storage infrastructure 112. Cold columns usually be held in storage infrastructure 112, but may be partially brought into HARP memory 304, e.g., for one time usage. In some embodiments, date columns in the Sorted-Compressed format will be held in the memory of host system 202 and accessed by the software running on host 202.

In general, there is a single entry point for HARP module 204 to identify all the database columns. In particular, as shown in FIG. 7, a root table 702 points to all the available table descriptors 704. The table descriptors 704 in turn point to their respective table columns 706. Each table stores multiple columns in the VA memory space. Each of these tables will now be further described.

As noted, root table 702 identifies all the tables accessed by HARP module 204. In some embodiments, each entry in the table takes 8 bytes. When needed, multiple Root Table blocks can be chained by a next pointer. The Descriptor Pointers in the root table 702 points to the individual table descriptors. The indices of the Descriptor Pointers also serve as the table ID. To simplify the hardware design, a CSR (Control Status Register) may be employed to store the Root Table information as long as the hardware accessible Table IDs and Descriptors' information is retained in HARP module 204.

Each database defined table has a table descriptor 704. All the table descriptors 704 may reside in the HARP memory 304. A table descriptor 704 may comprise different groups of data. A group may contain one or more columns. Within a group, the data is organized as rows. A group of data resides in a memory plane which is allocated to it. A data element in a particular plane has direct reference to its corresponding element in another plane. The relationship of the addresses among all the element pairs is the same arithmetical computation. The table descriptor is portable because the present invention utilizes a global virtual address space. In other words, when copying the table descriptor from one virtual memory location to another, all the information in the table is still valid.

In the C2 solution, the data structures of the database are architected to optimize database data processing in HARP hardware. All table columns/column groups, indices and meta-data are defined in a global database virtual address space (DBVA). A reserved DBVA section is allocated for table descriptors 704 as part of the meta-data. Table descriptors 704 include information about a table, such as the table name, number of rows, number of columns/column groups, column names, width(s) within a column group, etc. In addition to the information of data layout and access information in the VA space, the table descriptors 704 also have information about the compression types/algorithms used for each individual column. In the present invention, hardware can directly use this information to accomplish database queries and table element insertion, update, and deletion.

FIG. 8—Table Column Layout

FIG. 8 is now provided to provide further detail on the structure of a table in column-store format as employed by the C2 solution of the present invention. As shown, each database table is broken into multiple columns or column groups having a fixed width. Variable width columns are also supported using column hopping or a column heap structure with linked lists. In the C2 solution, a column group can have one or more columns packed together. Because of the simple arithmetic mapping or the single indirection in the companion column, the hardware and software of the present invention can easily access rows across the columns without any degradation in performance; thus, the C2 solution can provide the same functionality and benefits as known row store databases. Table and column descriptors may also be embedded in the MOPs and query tasks.

Of note, in the present invention, the columns or column groups possess an implicit row id (RID). A RID is considered implicit because it is not materialized as a part of a column or column group. Instead, each column and column group is designated a starting RID, which corresponds to an address in the global database virtual address space, which is then mapped to a physical address in HARP memory 304. Since each column and column group is a fixed width, the RID can provide the basis for arithmetically calculating the memory address of any data in the column or column group.

In some embodiments, all columns are packed together in the single DBVA. In addition, a meta-data structure may be employed to facilitate certain column accesses. For example, as shown, a row pointer primary key index may comprise a sorted list of primary keys and their associated row id (RID) in a column or column group. Of course, a B-tree index may be used as an alternative to this type of index.

In the present invention, two active sets of database regions are maintained, i.e., a main database region and an augment region for newly added data. Query processing operates on both regions and is accelerated by the HARP module 204. The augment region is utilized to hold new inserted items. Optionally, the augment region may be rolled into the main region. For example, as shown in FIG. 8, RIDs 1-n are the main region, while RIDs n+1, etc. comprise the augment region.

Deletion updates may be committed into the main region right away. To alleviate the drastic changes across all the columns in a table, the present invention may allocate a valid or invalid bit. A row deletion in a table, therefore, becomes a trivial task of setting the appropriate bit in every column group in the table.

FIG. 9—Example of a SQL Query

FIG. 9 shows one of the 22 TPC-H queries, query #3, and how it would be executed using the machine code database instructions. TPC-H queries are published by the Transaction Processing Performance Council (TPC), which is a non-profit organization to define benchmarks and to disseminate objective, verifiable TPC performance data to the industry. TPC benchmarks are widely used today in evaluating the performance of computer systems. This particular query is a shipping priority query to find the potential revenue and shipping priority of the orders having the largest revenue among those that had not been shipped of a given date. The market segment and date are randomly generated from the prescribed range, and BUILDING and Mar. 15, 1995 are the example here. This query is a complex multiple table join of three tables, CUSTOMER, ORDERS, and LINEITEM tables.

C2 Software 110 will decompose this query into 24 MOPs to send to HARP module 204, along with their dependency information, which establishes the topology of the dataflow from MOP to MOP. All MOPs are started and hardware processing begins in pipelined fashion, with each MOP's results being fed to one or more downstream consumers over one or more dedicated logical IMC connections.

The responsibility of the first MOP, ScanCol(0), is to reference HARP memory 304 to find all the customers in the CUSTOMER table who belong to the ‘BUILDING’ market segment, producing into IMC0 all matching CUSTOMER references in the form of one RID per qualified row. Revindex(1) then traverses a reverse index residing in 304, pre-built to relate customers to their one or more orders residing in the ORDERS table, outputting references to all orders made by the given customers. Because the CUSTOMER references are no longer necessary and to boost performance by reducing utilization of IMC transmission resources over IMC2, the ListProject(2) removes the original customer references after the reverse index join, leaving only the ORDER references. The ScanRPL(3) MOP then scans these orders' O_ORDERDATE column, retaining ORDER references only to those orders whose order date occurs before the date ‘1995-03-15’.

Progressing onward through IMC3, the dataflow entering Revindex(4) consists of ORDER table references (RIDs) which have satisfied all criteria mentioned thus far: each order was placed by a customer in the ‘BUILDING’ market segment before the date Mar. 15, 1995. To finish evaluating the WHERE clause of the illustrated SQL query statement, these orders must be qualified in terms of certain properties of their related line items.

The purpose of the Revindex(4) MOP is then to associate each of the qualifying orders to its one or more constituent line items from the LINEITEM table, returning appropriate references thereto. At this point, the flow contains a two-column tuple list relating ORDER references (RIDs) to LINEITEM RIDs, multicasting identical copies of these tuples into IMC4 and IMC5. ListProject(5) extracts only the LINEITEM RID column from the dataflow in preparation for ProjRpl(6), which extracts each line item's L_SHIPDATE column value, feeding these ship dates to IMC7. ListCompose(7) consumes IMC7 along with IMC5, executing a composition of the input lists to create a three-column tuple list where each tuple contains an ORDER RID, an associated LINEITEM RID and its ship date. ListSelect(8) consumes the composed list from IMC 8 and selects only those tuples having ship date older than ‘1995-03-15’, thus completing the WHERE clause requirements.

Again, at the output of ListSelect(8), the dataflow still logically appears as a three-column tuple list where each tuple relates an ORDER RID to one of its associated LINEITEM RIDs and that line item's ship date. It should be noted in this flow that multiple distinct LINEITEM RIDs may appear (in different tuples) with an identical ORDER RID, a definite possibility here since a single order may be comprised of an arbitrary number of line items in the target database and this query specifically requests only those line items satisfying the ship date criteria. The redundancy of ORDER RIDs in the list suggests an aggregation step will be needed to realize the SUM of the SQL select statement, but before that, some more data must be gathered and calculations done.

IMC9 and IMC10 both carry the output of ListSelect(8), identically. ListProject(9) extracts only the LINEITEM RID column from IMC9, passing that on to both ProjRpl(12) and ProjRpl(11), which fetch each referenced LINEITEM's L_EXTENDEDPRICE and L_DISCOUNT, respectively. Those procured extended price and discount data are then composed together by ListCompose(13) to form a two-column tuple to be carried via IMC17. ListTupleArith(14) implements the arithmetic process of computing (L_EXTENDEDPRICE*(1−L_DISCOUNT)) on a per-tuple basis before sending this arithmetic result to ListCompose(15). In the meantime, ListProject(10) extracts the ORDER RID column from the output of ListSelect(8), such that ListCompose(15) can make a two-column composition relating, within each tuple, an ORDER RID to its line item's arithmetic product.

The final hardware step to complete the query involves fully evaluating the SELECT clause, including its SUM aggregation function. The remainder of the MOP flow of FIG. 9, beginning with the output of ListCompose(15), is dedicated to this process.

AssocAccumSum(16) receives from IMC19 with each of the two-column tuples relating an ORDER RID to one of its line item's (L_EXTENDEDPRICE*(1−L_DISCOUNT)) product, computing a summation of these values independently for each distinct ORDER RID. For example, a given ORDER RID may appear twice in IMC19 (once in two different tuples), having two distinct LINEITEMs which satisfied all criteria thus far. Each of these LINEITEMs would have generated its own product in ListTupleArith(14), such that the aggregation process of AssocAccumSum(16) must sum them together. The result is a distinct sum of products over each distinct ORDER RID, realizing the SQL SUM aggregation function, here named REVENUE within the query.

Once the aggregation has completed for a given ORDER RID, ListProject(17) extracts the ORDER RID itself, passing it to ProjRpl(18), ProjRpl(19) and ProjRpl(20). These MOPs gather in parallel the referenced orders' O_ORDERDATE, O_SHIPPRIORITY, and O_ORDERKEY, respectively, while ListCompose(21) forms a two-column tuple consisting of O_SHIPPRIORITY and O_ORDERKEY. ListCompose(22) meanwhile forms a two-column tuple comprised of O_ORDERKEY and REVENUE. The final MOP, ListCompose(23), composes the two two-column tuple lists into a final four-column tuple list which satisfies the SQL query and its SELECT statement.

It should be noted in this example that the SQL query SELECT actually stipulates L_ORDERKEY. But an optimization may be applied here, knowing that O_ORDERKEY is functionally equivalent when used in this manner, thus avoiding the need to carry any LINEITEM RIDs beyond IMC11 or IMC12.

FIG. 10—Example of a Dataflow Through the HARP

In FIG. 9 we have described how an SQL statement gets mapped into a logical MOP DAG (directed acyclic graph) which gets executed in a dataflow fashion with IMC chaining between MOPs. FIG. 10 illustrates an exemplary dataflow through PEs 620 in HARP logic 302 for the same TPC-H SQL #3 query shown in FIG. 9. As noted, C2 Software 110 will decompose this query task into 10 PE stages to send to HARP module 204, along with their MOP and UOP instructions and dependency information.

Stage 1 is performed by Scanning PE 1002 is to find all the customers in CUSTOMER table that is in BUILDING market segment and passes the results (C_RIDs of matching customer records) in an IMC to Indexing PE 1004.

Stage 2 is a join operation of C_CUSTKEY=O_CUSTKEY performed by Indexing PE 1004 using a reverse index method. Each C_RID of Stage 1's matching customer records corresponds to an O_RID hitlist of ORDER table records, given a customer may place multiple orders. The results (O_RIDs) are passed in an IMC to Scanning PE 1006.

Stage 3 is performed by Scanning PE 1006 to read the O_ORDERDATE field of all the matching orders (O_RIDs) that Stage 2 outputs, compare for <‘1995-03-15’, and passes the results (O_RIDs) in an IMC to Indexing PE 1008.

Stage 4 is a join operation of O_ORDERKEY=L_ORDERKEY performed by Indexing PE 1008 using a reverse index method. Each O_RID of Stage 3's matching order records corresponds to an L_RID hitlist of LINEITEM table records, given an order may have multiple line items. The results (L_RIDs) are passed in an IMC to Scanning PE 1010.

Stage 5 is performed by Scanning PE 1010 to read the L_SHIPDATE field of all matching line items (L_RIDs) that Stage 4 outputs, compare for >‘1995-03-15’, and passes the results (L_RIDs) in 3 IMCs to Indexing PE 1012, 1014, and 1016.

Stage 6 is a column extraction/projection operation done by Indexing PE 1012, 1014, and 1016 to get L_ORDERKEY, L_EXTENDEDPRICE, and L_DISCOUNT column.

Stage 7 is a list merge operation of 2 columns (L_EXTENDEDPRICE and L_DISCOUNT) done by Indexing PE 1018.

Stage 8 is an aggregation operation of REVENUE of each L_ORDERKEY group, done by XCAM PE 1020 based on outputs of Indexing PE 1012 and 1018. As the SQL statement defines, REVENUE is calculated as the sum of (L_EXTENDEDPRICE*(1−L_DISCOUNT)). Note that even though the GROUP BY defines the group key as concatenation of L_ORDERKEY, O_ORDERDATE, O_SHIPPRIORITY, the group key is simplified to L_ORDERKEY since it is already a unique identifier. The output of XCAM PE 1020 is a pair list of group key (L_ORDERKEY) with its REVENUE.

Stage 9, done by Indexing PE 1022 and 1024, is a column extraction of O_ORDERDATE based on L_ORDERKEY output of XCAM PE 1020.

Stage 10, done by XCAM PE 1026, is a sieve (ORDER BY) operation of REVENUE, O_ORDERDATE to output top N groups with largest REVENUEs. These outputs are placed at a result buffer area in HARP memory 304, ready to be retrieved by DBMS software 114.

Explanation of the Global Database Virtual Addressing Scheme.

As noted, the C2 solution of the present invention can employ an arbitrarily large virtual address space (DBVA) to globally address an entire database. This addressing scheme is utilized to assist hardware acceleration, because it allows HARP module 204 and C2 software 110 to arithmetically calculate the location of any data in a database. FIG. 11 illustrates an exemplary logic flow of the addressing schemes employed and FIG. 12 illustrates a structure of the global database virtual address scheme of the present invention.

Referring now to FIG. 11, when a query is received from MySQL software 114, it is eventually submitted to query execution engine 412 for processing. At this level, execution engine 412 operates on the database using what are known as logical addresses. A logical address is utilizes the naming convention of the SQL query. For example, a logical address may consist of a database name, a table name, a column group name, and a column name which is then converted to a DBVA. Since it is a virtual address, the DBVA may be arbitrarily large, e.g., in excess of a petabyte.

The DBVA may then be converted to physical addresses of the data in storage 112 or in the memory of host system 202. For example, as shown, a storage manager 420 may have a mapping that converts a DBVA to a storage physical address (SPA). This allows for retrieval of data from storage 112. In addition, buffer manager 414 may convert the DBVA to a physical address in the memory of host system 202, for example, using a standard memory manager in the operating system running on host system 202. Such conversions are well known to those skilled in the art.

However, of note, the present invention may employ an extensible addressing scheme for one or more HARP modules 204. As noted, HARP modules 204 may comprise a relatively large memory, i.e., in excess of 256 gigabytes or more. In addition, the C2 solution may comprise nodes that have multiple HARP modules 204 and may also support nodes. Accordingly, the present invention may comprise a novel, layered virtual addressing scheme.

In one embodiment, each HARP module 204 translates the DBVA to a physical address (HPA) of HARP memory 304. For example, HARP module 204 may utilize a translation-lookaside buffer (TLB) for this translation.

Alternatively, especially in a multi-HARP module environment or federated system, each HARP module 204 may employ a secondary virtual address space (called an HVA) that is underlies the DBVA. Referring now to FIG. 12, in this embodiment, memory manager 418 may thus include a DBVA-HVA service that maps a DBVA address into yet another virtual address in the HVA. Memory manager 418 may then translate the HVA into a HPA using, for example, a TLB for the respective HARP memory 304.

This feature allows the present invention to continue utilizing a single global virtual address space for a database even where system 100 includes multiple HARP modules 204 or multiple nodes of HARP modules. Accordingly, systems of the C2 solution can continue to employ hardware-friendly addressing for hardware acceleration of the database operations regardless of the number of HARP modules 204 or the size of the database.

Use of Data Compression in the C2 Solution

In some embodiments, data may be stored in compressed column format on disk and memory. For maximum throughput, the data may be kept in memory as much as possible. When data need to be brought in from disk, the I/O may be parallelized with HARP operation. In some embodiments, the HARPs will operate directly on compressed data and the C2 software 110 may handle rewriting the queries appropriately and transforming the data between compressed and uncompressed formats when required.

In general, data compression is made transparent to the HARPs. Of course, not all columns may be compressed. Depending on the memory constraints, some columns may be left uncompressed disk and paged in whenever required. For such columns, an effort may be made to match the I/O rate to the HARP processing rate so that the I/O latency is minimized as much as possible.

In some embodiments, data may be in compressed form on disk, read in compressed format, but uncompressed when written to HARP memory 204 before letting the HARP operate on it. In cases where data needs to be paged in, if the accesses are not sequential, the I/O cost could be very high or sequential streaming might bring too much extraneous data in memory. In such cases, these transfers may be handled by SOPs in C2 software 110 rather than the HARPs. Of course, the optimizer 406 may performs these calculations and select between MOPs and/or SOPs for transferring in data. When the data is represented in compressed format, new data may be added to the table without having to reorganization of the entire table based on the data structures described herein.

In some embodiments, based on the nature of the data, different compression types may be chosen based on the profile of the data, column, or column group. C2 software 110 may utilize an input data profiler to sample the input files, determine heuristically the specific compression scheme and column/token widths for all the columns and then set them through a data definition. Metadata about the compression (compression type, tokens) may be stored in persistent storage 112. The types of compression used for character data can be as follows:

Token Based Compression

For columns representing names, addresses, comments etc., each individual column value may not be unique, but it is made up of fairly small set of ‘words’ (or tokens in general). In this case the set of tokens can be mapped to enums and each column value can be represented as a sequence of enums.

To be able to achieve this compression, delimiters are identified that can be used for the character set of the column. Tokens may be sequence of characters that are separated by delimiters. The set of delimiters may have 0 or more characters in the character set. In the limiting case where the set of delimiters is empty, the tokens are characters in the character set and no compression may be needed or may be deferred.

In token compression, a string is converted into a sequence of tokens (separated by delimiters which are valid tokens). Each token is assigned an immutable identifier (referred to as an index) and the compressed form of the string is the sequence of these token indexes. Each token may be also assigned a sort index (per collation sequence) which can be used for comparing tokens. This may be useful for character data where the amount of data itself might be large but the vocabulary is fairly small, such as, a comments column.

Delimiters could themselves be represented as an enum value or the token value could itself have some extra bits reserved to indicate the following delimiter. Different techniques for encoding the delimiters may produce different subtypes for compression. In explicit encoding for delimiters, the delimiter itself may be encoded and represented as a token in the compressed representation. In implicit encoding for a single delimiter, when there is a single delimiter, it may be optional to encode explicitly since it may be assumed that each token is separated by a delimiter. Extra bits in the token may also represent delimiters (multiple delimiters). In this compression type, the token encodes the delimiters that separate it from other tokens. For example, for 4 delimiters, it would take 2 bits to encode this so the last two bits in a token encoding may represent the delimiter that follows the token.

Enum Based Compression

Enum based compression is a token based compression when the entire string is treated as a single token. This may be useful for cases when the unique values for a column are within a fairly small set of known values, e.g., phone numbers, zip codes, a country or region, etc. For example consider a column (state CHAR(2)). The possible values for this column in ASCII character set may be fairly large but in the data, there will be at most 50 values. Thus, these can be represented using 6 bits instead of 16 bits.

Compression for Reduced Alphabet

In this scheme, each character can be treated as a token but the compression is a result of the fact that the set of characters found in the data is small. For example, data representing phone numbers and other numerical data only use characters 0-9, data representing DNA sequences only use characters A, C, G, U, T, and so forth.

Of note, once at least some of the data is expressed in terms of compressed values, the queries involving such data types may need to be rewritten. For example, X=a can be rewritten as X=c where c=Compress(a). Other operators may involve more complex rewrites.

Use of Dictionaries to Manage Tokens

In some embodiments, a single dictionary containing all the tokens in the database may be employed. A single dictionary may be useful in allowing query rewrites involving combination of columns. Alternatively, separate dictionaries for columns may be utilized. This scheme may be useful to achieve higher compression. In addition, dictionaries may be partitioned by character sets and column sizes.

To build the dictionary, the array of tokens may be sorted and an identifier assigned to the token to be the index of the token in the array. The ID for a token can be found using binary search on the array. This dictionary is order preserving since (ID(x)<ID(y))

(x<y). Once built, the dictionary could be saved persistently and reused at least until new tokens are added.

Dictionary Operations

A dictionary is generally maintained in terms of changes to the database, which might introduce new tokens in the dictionary. In some embodiments, the ID of a token is decoupled from the sort order of the token in anticipation of changes. Thus instead of assigning the index in the sorted array to be the index of the token, each token may be the next number in the monotonically increasing sequence of token numbers (index). Another array of sorted tokens can then be maintained, which defines the sort order of the tokens. The array indexed by the token ID then contains the index in the sort order array.

In some cases, the index may be an immutable index, which is immutable by giving the index in the order of entry into the dictionary. An immutable index can be used for equality comparison. For equality comparison, matching to an entry in the immutable index may a sufficient condition, but not a necessary condition. For example, in case-insensitive comparison tokens, ‘a’ and ‘A’ are same. However, their immutable index would be different.

In order to view the dictionary in a sorted order, a list of index-values into the dictionary may be created that is sorted on the values.

In order to rewrite the query containing constant values that are not in the dictionary (especially in the context of inequality comparisons), the rewrite may need refer to a sorted index that is not used in the dictionary. Accordingly, in some embodiments, the sorted index may be structured with gaps or holes. This allows the dictionary to change between the time when the query is optimized and rewritten, to when it is executed. Thus, the binding of the sorted index value need to happen during query execution generator. Addition of a token can cause reorganization in the dictionary, but not necessarily the mapping of the tokens to IDs itself.

Separating the dictionary from the sort order array may solve the problem of multiple collating sequences since a different sort order array for each collating sequence may be maintained. The arrays can then be maintained in HARP memory 204. Since, the dictionary is likely to be fairly small, it is not expensive to maintain these objects in memory.

Explanation of the Hardware-Friendly Data Structures and Indexing

The hardware-friendly data structures of the present invention are designed to maximize the efficiency of HARP modules 204. As noted above, the C2 solution of the present invention employs a column-store format database. In this format, a column group can have one or more columns packed together. Column grouping provides several benefits, such as spatial locality and access bandwidth efficiency.

The C2 data structures and indexing of the present invention provides the advantages of both column and row oriented databases. In the present invention, addressing columns or rows can be easily achieved without software assistance. For example, the present invention allows for column hopping based on simple arithmetic operations, which enables true hardware database processing.

In addition to the column-store format, several of the hardware-friendly data structures and indexing will now be explained. In particular, the following features will be explained: column hopping; forward indexing; hit lists; Reverse Indexing; group indexing; and entity service for tuple reconstruction.

Column Hopping

As noted, column hopping can have various uses, such as traversing variable width columns. With column hopping, the C2 solution can employ simple arithmetic mapping or single indirection in the companion column to access the same rows across different columns or column groups.

For example, in a table, a datum in a column can be addressed by a Unity Pointer (RID). The VA of a row in a column group is calculated as [base address]+[column_group_width]*[Unity Pointer]. When accessing a row or rows in a column group, the data pieces in the same row in other column groups are easily accessed. For example, memory addresses of other data pieces can be computed by arithmetic mapping; thus making the present invention hardware-friendly.

In common column groups, the Unity Size is based on the width of a column or column group. For heap regions, the Unity Size is the minimum allocable memory size. Thus, the hardware-friendly column hopping facilitates HARP indexing through columns or column groups without host system 202 software assistance.

Indexing Framework

Referring now to FIG. 14, an indexing framework of the present invention is shown. The indexing framework allows a user to store and access the metadata related to actual data that would help a caller to access data in quick fashion. The indexing framework can provide, for example, forward indexing; Reverse Indexing; and group indexing. These forms of indexing will now be further described.

Forward Indexing

Referring now to FIG. 20, an example of a forward index is shown. The forward index replaces a foreign key (FK) value with an actual RID (Unity Pointer) from a first table (Table 1) of the foreign table (Table 2). With forward indexing, the related row (i.e., RIDx and RIDy of Table 2) can be addressed directly without B-Tree searching of the FK to the foreign table. The RID also allows access to the fields in any of the column groups. The uniform RID scheme also allows tables to be relocated without changing any table contents.

Reverse Indexing

Reverse Indexing enables primary keys in a table A to be mapped directly to a list of rows with matching foreign keys in table B. Unlike forward indexing, Reverse Indexing usually has one-to-many mappings. Similar to forward indexing, only the row IDs to table B are stored.

A Reverse Index of the present invention allows use of a foreign key—primary key relationship. The Reverse Index internally maintains a hit list structure which can be used to map primary key and all related RIDs where that primary key occurs in the table having the foreign keys.

Hit Lists

Referring now the FIGS. 15-16, examples of reverse indexing are shown as a hit list. The hit list is a customized hash map, which is used to store mappings between values and RIDs that contain those values. Referring now to FIG. 15, an example hit list is shown comprising a hit list Head (HLH) and a hit list Extension (HLE).

Example of Use of a Reverse Index and Hit List

In the example shown below, values in the ORDERS.Customer_SID column appear in the CUSTOMER.SID column. The SID column is the primary key in CUSTOMER table. If given a SID value, all rows in the ORDERS table that reference the given SID value are desired, this relationship information can be stored in a Reverse Index.

In the present invention, the Reverse Index is implemented as a special column of the CUSTOMER table. This special column stores RIDs from the ORDERS table. For example, as shown, a few RIDs are stored in the special column in-place, and the remaining RIDs are stored in another independent, overflow column.

Order_id Row ID Customer Name Xyz 0 sibsankar Abc 1 sibsankar Aaa 2 krishnan Bbb 3 sibsankar

Which Customer Name Row ID orders Sibsankar 0 0, 1, 3 Krishnan 1 2,

In the above table ‘which orders’ is a Reverse Index column in the Customer table, which stores RIDs from the Orders table. Each row of the Reverse Index column may be composed of one or more hit list nodes. For example, a Reverse Index column can store hit list head nodes and an overflow column for an extension to the hit list.

Referring now to FIG. 16, the hit list node data structure is shown. The RID points to a row of the destination table. Next ID stores the RID of next hit list node and valid/invalid information. In addition, as shown in FIG. 18, the hit list may be extended using a reverse index to a heap region (Hitlist Heap) to accommodate variable length data. Of note, in the heap, entries may be linked together in a linked-list array to allow for extensibility of any length data.

B-Tree Indexing

In some embodiments, B-Tree indexing is used for special indexing, sorting, Augment Data Structure ordering. The B-Tree may be a standard implementation of a B-Tree data structure, which is used to store mappings between key-value pairs. In the present invention, the value paired with the hit list key is the RIDs that contain the key. Thus, the B-Tree can enforce uniqueness and return an error if the key being inserted is already present.

Group Index (GI)

Referring now to FIG. 17, a group index and VA range table are shown. The group index is used for indexing a column that has values that can be ‘grouped’. A typical use of a Group index is to index strings, text, date ranges, and data having enumerated types, e.g., Zip code, states, etc.

The group index may go further in optimizing access to data by trying to store some metadata information using the hit list data structure. This metadata information can be updated during insertion and may be of help during searching.

The Group index may be implemented using a hit list, a Group Item Table (GIT), and a VA Range (VAR) table. The hit list structure was described previously, and thus, the GIT and VAR tables will now be described.

In the GIT, a group item is any entry in the column that is indexed using a group index. A GIT contains a row for every unique group item encountered in the column to be indexed. For easy searching of a group item, the group item is inserted into the GIT table in an ordered fashion.

For example if there are 3000 words in the dictionary, the GIT table has 3000 rows. A word with numeric value 15 is inserted into the 15^(th) row and word with numeric representation 200 is represented into the 200^(th) row. This makes the lookup time to a group item constant. Since not all words in the dictionary are in a text column. In many situations, the GIT table is usually sparse and many rows could end up being ‘null’. For a text column that is indexed using a group index, the GIT contains a row for every word encountered in the base table's text column. For a date column that is indexed using a group index, the GIT contains a row for every date entry encountered in the base table's date column.

VAR Tables

The virtual address range (VAR) table captures the VA range occupied for a single group entry in the HLE table. A group id can occupy multiple ranges of VAs in the HLE. For example, multiple VA range entries (1 row in VAR table) can linked together using next_RID pointer.

In some embodiments, a VA range is allocated for every group item. In addition, there may be free space (e.g. 1% free space) left towards the end of every VA range to accommodate subsequent inserts of new group items.

Entity Service (for Tuple Reconstruction)

In the present invention, an entity service is provided to serve the data structure and indexing of the C2 solution. Referring now to FIG. 13, this entity service comprises two main components: a tuple service and the indexing framework described above.

The tuple service (TS) acts as an interface for a caller to access the data in a different fashion or granularity. The TS can serve data in the form of columns or rows. The TS can also serve data in compressed and uncompressed format.

For example, the C2 software 110 may use the tuple service (TS) to access and stitch the column data into row data. In general, the tuple service does not interpret data contents; it merely puts together column values into a row. The tuple service can also interact with C2 software 110 for fetching the data.

A variable length column (VLC) heap may be part of the entity service, which is used to store uncompressed variable length data. For example, a user may thus create a column with a varchar property and set it to remain uncompressed. A user or caller can update the VLC using different VLC interfaces/APIs. A VLC heap may be a heap of rows that are linked in sequential fashion. If a row ends but data still exists for the current entry, the VLC interface will make sure that it spans the required number of rows to get complete data.

Replicated Reordered Columns

Replicated reordered columns (RRCs) provide a data structure that reorders data so that it can be sequentially retrieved from storage. For example, RRCs may be useful with date information that is compressed into ranges. In date range compression, each date is indexed as one entry in a table. In some embodiments, each entry contains two pointers pointing to a start and an end of date-ordered RRC's row IDs (DRIDs), which contain the Unity Pointers (default ROWID) of the associated table. Once the date range is obtained, the related ROWIDs and RRC data can then be sequentially accessed from storage 112.

In addition, given the C2 compression scheme of the present invention, there is no need to bring the entire column into HARP memory 304. Instead, only the portion of the column in the date range is fetched. In some embodiments, HARP modules 204 will likely not maintain the compressed date range table. Instead, the host system 202 will determine the ranges, and let the HARP modules 204 access the RRCs as independent tables. As another example, RRCs may be employed as a remapping data structure to maintain an immutable index.

FIG. 19—Word Dictionary Compare

In the present invention, a word dictionary is employed to facilitate comparison and scanning of text. In particular, the text may be compressed into words and indexed by a data structure known as a word dictionary. This word dictionary may comprise a list of compressed strings. Each number in a row represents a word in the string. Each row may have a constant number of words and every row may have the same size throughout the entire column.

The dictionary also may comprise: sorted indexes—pointers pointing to the entries in the Reverse Index structure; and a word list—each entry has a one to one mapping to a word. The dictionary table is filled as new words are discovered regardless of word order. In some embodiments, the token value (index) is given as a monotonically increasing number.

As noted, the word dictionary may employ a Reverse Index. In some embodiments, odd positions (index numbers) are used. Even index numbers are then reserved for in between non-existent word compares. Each entry thus points back to an entry in the dictionary structure described above.

In the present invention, words are identified and added to the dictionary for each new word along with a new token value. A row size of the dictionary is based on the maximum word count and the total number of words in the dictionary.

For the strings which have fewer words, they may be padded with NULL words. To ease word comparisons and avoid renumbering the word index (token value) for new word additions, a sorted Reverse Index table is built. The pointers to the Reverse Index are stored in a sorted index column while the pointers to the dictionary entry are stored in the Reverse Index table.

In database queries, it is customary to search for entries containing one or more words. To search one word in the dictionary, a binary search is performed starting on the Reverse Index table. Following the pointer to the word entry, a word compare is performed with a given word. If the word is greater than the word in the current entry, a binary search is conducted in the second half of the Reverse Index table. Otherwise, a binary search is conducted on the first half of the Reverse Index table. These steps are then applied recursively to that half and so forth. Once the word is found, the word index (i.e., token number) is used to search the compressed strings.

Because a number is being searched instead of a sequence of characters, the C2 hardware of the present invention can execute the word search in parallel (compare many tokens not characters). For multiple word matching, for example, HARP logic 302 can search the word numbers (tokens) individually, then search the tokens in the list of compressed strings.

For words that are not in the dictionary, a non-equality compare can be converted to one or many equality compares with the help of a Reverse Index table. As new rows are added, a new token can be assigned by simply taking the current dictionary count+1 as the new token. The Reverse Index table is also updated. Generally, the dictionary size can be small. Thus, in some embodiments, non-used words are left in the dictionary until the database is rebuilt.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. For example, DB formats of various embodiments may include:

FLOAT—compressed double/float number;

INT—compressed integer number;

DICT STR—dictionary compressed string;

ENUM—compressed enum form;

PHONE—compressed phone number;

CMP_STR—string with fewer digit character set;

DATE—compressed date; and

RAW—raw data (uncompressible).

Except for RAW and CMP_STR, the compressed formats may have uniform size in a column, and thus, are accessible through indexing.

Column data with irregular sizes may be stored in a heap region. In a column group, pointers are then stored to point to the data in the heap. In addition, for dates, the present invention can provide a date attribute column for data that is likely to be accessed based on a date range. Since storing dates in a table costs memory space, the present invention may use date ranging. Date ranging enables fast date related query by removing the overhead of filtering on dates for individual rows.

It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. 

What is claimed is:
 1. A computer-implemented method of relating data across tables in a column-store database, wherein said method is implemented at least partly by one or more processors, said method comprising: determining a row identifier of a first tuple in a first table; reading an index at a row corresponding to the row identifier of the tuple of the first table to obtain another row identifier of a second tuple of another table, wherein reading the index comprises calculating a pointer to another column serving as an extension to the index; and determining data related between the first and second tuples based on reading a memory at an address calculated from the row identifier in the index, wherein the memory is coupled to a dataflow accelerator processor comprising dataflow architecture hardware configured to read the memory at the address calculated from the row identifier in the index and to execute database machine code instructions using the memory at the address calculated from the row identifier in the index.
 2. The method of claim 1, wherein reading the index comprises calculating an address in a memory based on the row identifier of the index.
 3. An apparatus comprising one or more processors configured to: determine a row identifier of a first tuple in a first table; read an index at a row corresponding to the row identifier of the tuple of the first table to obtain another row identifier of a second tuple of another table wherein reading the index comprises calculating a pointer to another column serving as an extension to the index; and determine data related between the first and second tuples based on reading a memory at an address calculated from the row identifier in the index, wherein the memory is coupled to a dataflow accelerator processor comprising dataflow architecture hardware configured to read the memory at the address calculated from the row identifier in the index and to execute database machine code instructions using the memory at the address calculated from the row identifier in the index.
 4. A non-transitory computer readable storage medium comprising storing at least computer executable instructions for configuring a processor to: determine a row identifier of a first tuple in a first table; read an index at a row corresponding to the row identifier of the tuple of the first table to obtain another row identifier of a second tuple of another table wherein reading the index comprises calculating a pointer to another column serving as an extension to the index; and determine data related between the first and second tuples based on reading a memory at an address calculated from the row identifier in the index, wherein the memory is coupled to a dataflow accelerator processor comprising dataflow architecture hardware configured to read the memory at the address calculated from the row identifier in the index and to execute database machine code instructions using the memory at the address calculated from the row identifier in the index.
 5. A computer-implemented method of searching for data in a column-store database, wherein said method is implemented at least partly by one or more processors, said method comprising: identifying a group of data; determining a row identifier corresponding to the group of data in a first table; reading an index at a row corresponding to the row identifier of the group to obtain a set of row identifiers of at least one tuple of another table; reading an additional column having entries that are reordered into a sequential input/output pattern of access; and retrieving data in the group based on reading memory at addresses calculated from the at least one row identifier in the index, and wherein the memory is coupled to a dataflow accelerator processor comprising dataflow architecture hardware configured to read the memory at the address calculated from the row identifier in the index and to execute database machine code instructions using the memory at the address calculated from the row identifier in the index.
 6. The method of claim 5, wherein identifying the group to which the data is a member comprises identifying a range of dates related to the data.
 7. The method of claim 5, wherein identifying the group to which the data is a member comprises identifying a token in the data.
 8. The method of claim 7, wherein identifying the token in the data comprises identifying a sequence of characters surrounded by at least one delimiter.
 9. The method of claim 5, wherein identifying the group to which the data is a member comprises identifying an enumerated range to which the data is a member.
 10. The method of claim 9, wherein identifying the enumerated range comprises identifying the data as a zip code.
 11. The method of claim 9, wherein identifying the enumerated range comprises identifying the data as comprising a phone number.
 12. The method of claim 9, wherein identifying the enumerated range comprises identifying address information in the data.
 13. The method of claim 9, wherein identifying the enumerated range comprises determining whether the data is within a range of predetermined values.
 14. The method of claim 5, wherein reading the additional column comprises: reading a set of pointers from entries in the additional column that indicate starting and ending row identifiers; and retrieving only the entries from the column that are within the starting and ending row identifiers.
 15. The method of claim 14, wherein retrieving data in the group comprises sequentially fetching data from storage based on addresses derived from the starting and ending row identifiers.
 16. An apparatus comprising one or more processors configured to: identify a group to which the data is a member; determine a row identifier corresponding to the group in a first table; read an index at a row corresponding to the row identifier of the group to obtain a set of row identifiers of at least one tuple of another table; read an additional column having entries that are reordered into a sequential input/output pattern of access; and retrieve data in the group based on reading memory at addresses calculated from the at least one row identifier in the index and wherein the memory is coupled to a dataflow accelerator processor comprising dataflow architecture hardware configured to read the memory at the address calculated from the row identifier in the index and to execute database machine code instructions using the memory at the address calculated from the row identifier in the index.
 17. A non-transitory computer readable storage medium storing at least: program code for identifying a group to which the data is a member; program code for determining a row identifier corresponding to the group in a first table; program code for reading an index at a row corresponding to the row identifier of the group to obtain a set of row identifiers of at least one tuple of another table, and reading an additional column having entries that are reordered into a sequential input/output pattern of access; and program code for retrieving data in the group based on reading memory at addresses calculated from the at least one row identifier in the index, and wherein the memory is coupled to a dataflow accelerator processor comprising dataflow architecture hardware configured to read the memory at the address calculated from the row identifier in the index and to execute database machine code instructions using the memory at the address calculated from the row identifier in the index. 